http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-19929172-A1

Outgoing Links

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filingDate 1999-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7e4f525ea91e8ef0f445e0d152ff684a
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publicationDate 2001-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber DE-19929172-A1
titleOfInvention Integrated memory
abstract The integrated memory has a first address path, via which address connections (ADR) are connected to first selection lines (CSL) of a first group (G1) and which has corresponding first lines (L1) and a first decoder circuit (DEC1). It also has a second address path, via which the address connections (ADR) are connected to first selection lines (CSL) of a second group (G2) and which has corresponding second lines (L2) and a second decoder circuit (DEC2). The first decoder circuit (DEC1) is faster than the second decoder circuit (DEC2). The first lines (L1) have a longer signal delay than the second lines (L2).
priorityDate 1999-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 24.