| abstract |
The integrated memory has a column decoder (CDEC) for decoding column addresses and for addressing corresponding bit lines (BL). It also has a first column address bus (CADR1), via which first column addresses are transmitted to the column decoder, and a second column address bus (CADR2), via which second column addresses are transmitted to the column decoder. The column decoder addresses bit lines that correspond to the first and second column addresses supplied to it. |