| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-402
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1045 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7393 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-739 |
| filingDate |
1996-08-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c9de40fdba40e626a6ec67d9930cdec2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1b9859ee0e184f7beed1690aba2dcbaa |
| publicationDate |
1997-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-19632110-A1 |
| titleOfInvention |
Semiconductor device and method of manufacturing the same |
| abstract |
A semiconductor device has a semiconductor layer (5) which is formed on an insulating layer (3) on the main surface of a semiconductor substrate (1) and which has an element forming region for forming an element with an insulated gate transistor (30) section and another element forming region for forming another element (40, 50). The layer (5) has a trench (63) surrounding the periphery of the element forming region for isolating this region from the other element forming region. The insulated gate transistor (30) has separate source and drain regions (9, 11) formed at the surface of the layer (5), the source region (9) being located at the layer surface in the element forming region and surrounding the periphery of the drain region (11). Also claimed is a process for prodn. of the semiconductor device. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-19811604-B4
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102006058228-B4 |
| priorityDate |
1995-08-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |