http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-19546168-C1

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06T7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G10L15-28
filingDate 1995-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1997-02-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d6b91906f7e013966a9f4b87e445de8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1ebb18c1e404a10e262d3a3a28b4d9a6
publicationDate 1997-02-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber DE-19546168-C1
titleOfInvention Digital signal processor arrangement for comparing feature vectors and their use as well as the associated operating method
abstract The processor allows comparison of indication vectors using at least one accumulator/multiplier processor core (REK), for calculation of a test indication vector, fed to a data memory (DSPE), with a given word width and a test memory (PSP) with a second word width. The core processor, the data memory, the test memory and a processing stage (REW) for comparing the test indication vector with a reference vector are coupled together via a connection bus (DBUS) for transmission of data and addresses.
priorityDate 1995-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 20.