| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_33a51bb9cd76252dfda6da07322eb4bd |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-2043 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-2028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1658 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-177
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-14 |
| filingDate |
1995-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
1997-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_26796d8ebdd5ed5769943d360ea8c05f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e3e5b12721586ade17bde2c0b55592f4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8f256fc187d595334795642217bc6531
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1d13eb8ebf575d0ce0cef362c97a19d9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_73fc768621598387a7a7c55af4742958
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3e73d752cbe9b5429a80cbb670423a4b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8ea6fc979a0b96094bbdc03b4abbe7f7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cedefbeed0a5e9a07e58462f644d0c28 |
| publicationDate |
1997-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-19525013-C2 |
| titleOfInvention |
Multiprocessor system |
| abstract |
A symmetric multiprocessor system connecting a plurality of CPUs by a common bus initializes itself while defective CPUs are set aside to use only the remaining CPUs when the power is turned on, thereby maintaining the predetermined CPU numbers and giving a minimum influence with the existing software thereof. The multiprocessor system includes an identifier setting register to designate in a predetermined order the CPU numbers only to normal CPUs, and a reset controller to cut off the defective CPUs from the common bus. The multiprocessor system can automatically start re-setting up where the defective CPUs are detected during the processing of setting-up based on the time-out detection, can release an abnormal state of the hardware, and can control the setting-up processing in use of any CPU based on the level of a reset status input port and contents of a reset information register. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-19983975-B3
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6714996-B1 |
| priorityDate |
1994-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |