http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-112017000200-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-0944 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-20 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H10B10-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 |
| filingDate | 2017-01-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2023-01-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aa65433cb020f284926f7bab91cbe17c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1a95fbcd5947447da350740a3f437ac8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_17ea876c0cad0339b42e3cc30b4faf72 |
| publicationDate | 2023-01-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-112017000200-B4 |
| titleOfInvention | ULTRA DENSITY VERTICAL TRANSPORT FET CIRCUITS |
| abstract | Logic circuit comprising: a first vertical transport field effect transistor and a second vertical transport field effect transistor each having source/drain regions (2, 3; 4, 5) on vertically opposite sides of a gate structure (7; 107a; 107b) and a vertical fin (6; 9; 106a; 106b) extending vertically upwards with respect to a support substrate of a vertical inverter from a lower source/drain region (2; 4) to an upper drain/source region (3; 5); one or more gate structures (7); wherein logic circuit components are present on at least three different and distinguishable vertical levels, a field effect transistor (FET) level having a horizontal level passing through the fins of the first and second vertical transport field effect transistors, a first circuit level (M1) and a second circuit level (M2); wherein the first circuit level (M1 ) comprises at least one horizontal level through at least one conductive element (10) providing an input voltage for the one or more gate structures and another conductive element (36) providing an output voltage of the logic circuit ; the second circuit level (M2) having a horizontal plane through at least one conductive element forming a conductive bridge from an N-output to a P-output of the vertical transport field effect transistors; and wherein the second circuit level (M2) is arranged vertically above and separated from the first circuit level (M1) and wherein the first circuit level (M1) is arranged vertically above the field effect transistor (FET) level and is separated from this in which: the logic circuit comprises a NAND logic gate (200) having three separate gate structures (201) and a plurality of vertical transport field effect transistors; or the logic circuit comprises a logic gate selected from the group consisting of one C PP vertical transport inverter (1), two C PP double width vertical transport inverters, two C PP NOR vertical transport logic gates (100) and Three-C PP NAND vertical transport logic gates (200) and combinations thereof, where: the two C PP double width vertical transport inverter provides a function equivalent to a three C PP inverter in which the field effect transistors are planar; and wherein the three C PP NAND vertical transport logic gate provides a function equivalent to a five C PP logic gate in which the field effect transistors are planar. |
| priorityDate | 2016-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 41.