| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L2209-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L2209-34 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09C1-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L9-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L9-0631 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-71
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L9-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-30 |
| filingDate |
2016-08-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_50d29a3a5d3d9e95960d05221a0bea08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b475ee8def63d864acc069df08afb85e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c4336f106f095c2176f5d664306503ef
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9227c138a6f245fa63e6ededb5417c3e |
| publicationDate |
2018-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-112016004364-T5 |
| titleOfInvention |
SMS4 ACCELERATION PROCESSORS WITH ROUND CONSTANT PRODUCTION |
| abstract |
A processing system includes memory and processing logic operably coupled to the memory. The processing logic identifies one or more constant bits of an output bit sequence. The processing logic creates multiple variable bits of the output bit sequence. The processing logic generates the output bit frequency containing the identified constant bits and the created multiple variable bits. |
| priorityDate |
2015-09-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |