http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-112015006934-T5
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2009-4557 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2009-45591 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2009-45566 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-5027 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-45558 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-455 |
| filingDate | 2015-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_14142d637e05b35ee6ae0291a333c948 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3d69192cf0a1d478e665c6cf8ece1bf2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_35d68319dacb1faac588c354888ed9c0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_acf1741239e4cec6c93fbec2079de0aa |
| publicationDate | 2018-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-112015006934-T5 |
| titleOfInvention | Nested virtualization for virtual machine exits |
| abstract | Memory security technologies are described. An exemplary processing device includes a processor core and a memory controller coupled to the processor core and a memory. The processor core may determine that an exit condition for transferring control of a resource for a processor core has occurred from a first virtual machine monitor (VMM) to a second VMM. The processor core may also determine if a virtual machine control structure (VMCS) control connection pointer is valid. The processor core may also determine if a reason value corresponding to the control VMCS connection pointer is set. The processor core can also determine if the reason value is set to zero. The processor core can also determine if an exception bit corresponding to a specific exception type of a reason value is set. The processor core may also transfer control of the resource from the first VMM to the second VMM. |
| priorityDate | 2015-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.