http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-112012004932-T5

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filingDate 2012-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_201f76e45dcff7217058823f62cb8e1c
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publicationDate 2014-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber DE-112012004932-T5
titleOfInvention SOI-FinFET with recessed fused ribs and layer for improved voltage coupling
abstract FinFETs and methods of making FinFETs with a recessed stress layer. One method includes providing an SOI substrate with fins, forming a gate over the fins, forming an offset spacer on the gate, epitaxially growing a thin film to fuse the fins, depositing a dummy spacer around the gate and recessing the fused epitaxial thin film. A silicide is then formed on the recessed fused epitaxial thin film, followed by deposition of a stress thinning layer over the FinFET. By using a recessed and fused epitaxial layer process, a MOSFET can be formed with a vertical silicide (i.e., perpendicular to the substrate). The vertical silicide improves the propagation resistance.
priorityDate 2011-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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