http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-112012003231-T5

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filingDate 2012-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_687f8505a168bd6f3efba038565c532b
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publicationDate 2014-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber DE-112012003231-T5
titleOfInvention CMOS transistor with epitaxial extension
abstract In a semiconductor layer, a pair of trenches including a horizontal step are formed by forming a pair of first trenches having a first depth d1 around a gate structure on the semiconductor layer, forming an exchangeable spacer 58 around the gate structure, to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth d2 that is greater than the first depth d1. The replaceable spacer is removed and selective epitaxy is performed to form an integrated epitaxial source and source extension region 16 and an integrated epitaxial drain and drain extension region 18. After a deposition and a dielectric planarization layer 70 and a subsequent removal of the gate structure and a lateral extension of the gate cavity 59 via the epitaxial source 16 and drain extension region 18, a replacement gate structure can be formed. Alternatively, a contact layer dielectric layer may be deposited directly on the integrated epitaxial regions and contact via structures may be formed therein.
priorityDate 2011-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 22.