| abstract |
Multi-layer integrated circuit integration techniques are provided. In one aspect, a method of manufacturing an integrated circuit is provided. The procedure includes the following steps. A substrate is provided. On the substrate, a plurality of interconnect layers are formed, which are arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, over the given interconnect layer in FIG and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if any, under the given interconnect layer in the stack. At least one transistor is formed on a topmost layer of the stack. |