| abstract |
Technologies for the formation of transistor devices are disclosed which have a reduced parasitic contact resistance compared to conventional devices. In some example embodiments, these technologies may be used to implement the contacts of MOS transistors of a CMOS device, with an inter III-V semiconductor material layer between the p-type and n-type source / drain regions and their associated metal contacts are provided to significantly reduce the contact resistance. The III-V semiconductor material layer may have a small band gap (e.g., less than 0.5 eV), and / or be otherwise doped to provide the required conductivity. These technologies can be applied to a variety of transistor architectures (eg planar transistors, ripple transistors, and nanowire transistors), including strained and unstressed channel structures. |