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filingDate 2010-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2018-05-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ddfe82f9d560e65348c36db186c95db7
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publicationDate 2018-05-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber DE-112010005236-B4
titleOfInvention Backside pseudo plug for 3D integration
abstract Semiconductor structure comprising: a substrate having a semiconductor layer and a dielectric connection layer, wherein at least one semiconductor unit is mounted at an interface between the semiconductor layer and the dielectric connection layer; a via structure through the substrate (TSV structure) embedded in the substrate, the TSV structure comprising a conductive material and extending at least from the interface to a back surface of the substrate; and at least one backside pseudo plug embedded in the substrate, the at least one backside pseudo plug extending from the back surface to a depth into but not beyond the substrate, the depth being less than a vertical distance between the back surface and the interface, and wherein the at least one rear pseudo plug has no electrical contact with a conductive structure comprising a conductive area farther from the back surface than the depth, and - Has no electrical contact with a conductive structure which extends contiguous to the conductive region, which is farther away from the back surface than the depth.
priorityDate 2010-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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