| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02063 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate |
2008-02-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c89d01028af3d9d51882cc24fe4a01a2 |
| publicationDate |
2009-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-112008000100-T5 |
| titleOfInvention |
Method of forming transistor contacts and vias |
| abstract |
Method, comprising: Applying a dielectric layer to a substrate having a transistor; Etching a first opening in the dielectric layer contacting a gate stack of the transistor; Applying a sacrificial material in the first opening; and Etching a second and a third opening in the dielectric layer contacting a source and a drain region of the transistor, wherein the second and third openings are etched after the first opening is etched. |
| priorityDate |
2007-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |