| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36f8253f3d0d59bcd9259217d4385d10 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7923 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2003-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c193c08403b3f27bc512ea7c70cbd77b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8b7f127b74d5c7e6a2a772c6ac6dcb08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_70afb84d68125e2270511b014ae4dc6f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed2dcdf47d70df015453295fcd506afd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_027adb15c78337255460b0052f914135
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9ba820b839e59454a7b70fc278d8990b |
| publicationDate |
2005-02-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-10352641-A1 |
| titleOfInvention |
Charge trapping memory cell and manufacturing process |
| abstract |
Anfor batch trappingnprovided memory layer sequence with a memory area (8) betweennBoundary layers (7, 9) are formed on overhanging flanks (6) of a gate electroden(5), wherein the memory area (8) at the lower gate edgenin the form of a veinnone between the respective source / drain region (2) and thenChannel region (3) existing interface (10) extends. |
| priorityDate |
2003-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |