http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-10335391-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36d1d9c59848bff6ad5f55923d1290f5 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-43 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-105 |
| filingDate | 2003-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1fcfbe42947546f3125815c11ca7c696 |
| publicationDate | 2004-06-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-10335391-A1 |
| titleOfInvention | Manufacturing process for a flash memory device |
| abstract | Flash memory overwrite endurance is improved. A first interlayer insulating layer (10) is formed on a flash memory cell, which is formed in a memory element zone on a semiconductor substrate (100). Instead of a short-term heat treatment by means of lamp annealing, furnace annealing is used as a heat treatment after an NSG layer (16), which is an uppermost layer of the first intermediate layer insulation layer (10), has been formed. Accordingly, a load applied to the flash memory cell is released and the overwrite endurance is improved. In addition, the furnace annealing is added after a first and a second aluminum wiring (21 and 31) have been formed. In addition, when a second and third interlayer insulating layer (20 and 30) are formed, a deposition temperature of TEOS plasma layers (23 and 33) is set so that it is equal to the temperature of HDP layers (22 and 32). Accordingly, the overwrite endurance of the flash memory cell is improved. |
| priorityDate | 2002-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.