| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d231147f38595bbe3114b758cba4a298 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2254 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-109
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1087
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1078
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1051
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-406 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-406
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00 |
| filingDate |
2003-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c9254236785e03a6d452bb874cc5dc88 |
| publicationDate |
2005-06-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-10326925-A1 |
| titleOfInvention |
Storage system and control method therefor |
| abstract |
OnenMemory system and a control method allow for the samenstable operation at high frequencies without the problem of radiant interference.nIn the memory system, a plurality of DRAMs are on each of a pluralitynModules are provided, and each DRAM is equipped with a memory controllernconnected by data lines and clock lines. The clock lines havena topology that is used exclusively for each modulenwhilenthe data lines have a topology to connect to their associated onesnHave DRAMs on each module. Command / address lines also havena topology similar to that of the clock lines. In this casenbe data signals that are fed through the data lines,nand clock and command / address signals,nthrough the clock lines and the command / address linesnsuppliednare at different clocks / timings between thenDRAMs and the memory controller transferred.nFor this purpose, the DRAMs and the memory controller with circuitsnto customize the clocks. |
| priorityDate |
2002-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |