| abstract |
A resistive random access memory having a memory cell containing a resistive element having a resistance that varies in response to a write operation and storing data in accordance with the resistance of the resistive element, a reference resistive element having a resistance set to a first value, a voltage line that is biased during a a first writing operation in which the resistance of the resistive element is changed from a second value, which is higher than the first value, to the first value, is set to a first voltage, and a voltage control circuit arranged between first ends of the two resistive elements. The voltage control circuit adjusts a value of the first voltage supplied from the voltage line to reduce a difference between currents flowing through the two resistive elements during the first writing operation, and supplies the adjusted first voltage to first ends of the two resistive elements. |