| abstract |
A gate driver circuit (13) of reduced size and a display device (1) having the gate driver circuit (13) are presented. The gate drive circuit (13) includes a plurality of stage circuits (ST(1), ..., ST(n)). Each tap circuit supplies a gate signal to each of the gate lines (15) arranged in a display panel (10) and includes an M node (M), a Q node (Q), a QH node ( QH) and a QB knot (QB). Each stage circuit includes a gate signal output module (514) configured to operate based on a Q node (Q) voltage level or a QB node (QB) voltage level to first through jth Gate signals (SCOUT(i), SCOUT(i), SCOUT(i+1), SCOUT(i+2), SCOUT(i+3)) based on the first through j-th sampling clock signals (SCCLK(i) , SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) or a first low-potential voltage (GVSS1). |