| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1079
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-085 |
| filingDate |
2021-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d4484247963163cff69c0262a54dfed8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_708c8fdae1f0b078e4d0fbc0525addeb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4fc0025682c8adb27c90d36fb33f1e1a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5e36321352ae757f4cb99cd84605921
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a669c293dce60354a1d2c6edca85c3e3 |
| publicationDate |
2022-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102021121844-A1 |
| titleOfInvention |
Fabrication of gate-all-around integrated circuit structures with additive metal gates |
| abstract |
Gate all-around integrated circuit structures with additive metal gates are described. For example, an integrated circuit structure includes a first vertical array of horizontal nanowires and a second vertical array of horizontal nanowires. A first gate stack is over the first vertical array of horizontal nanowires, the first gate stack including a P-type conductive layer having a first portion surrounding the nanowires of the first vertical array of horizontal nanowires and a second portion juxtaposed laterally extending from and spaced from the first portion. A second gate stack is over the second vertical array of horizontal nanowires, the second gate stack comprising an N-type conductive layer having a first portion surrounding the nanowires of the second vertical array of horizontal nanowires and a second portion adjacent to the second portion of the conductive layer is P-type and is in contact with it. |
| priorityDate |
2020-09-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |