| abstract |
A semiconductor device (100) includes a device isolation layer (110) on a substrate (101); pattern groups (PG1, PG2, PG3) including fin patterns (105A, 105B, 105C) extending in a first direction (X); and gate structures (160) extending in a second direction (Y) to intersect the fin patterns (105A, 105B, 105C). A first pattern group (PG2, PG3) among the pattern groups (PG1, PG2, PG3) may include first fin patterns (105B, 105C). At least a portion of the first fin patterns (105B, 105C) may be arranged at a first pitch (P1) in the second direction (Y). The first pattern group (PG2, PG3) may include a first planar portion (FP1, FP2) extending from a first recess portion (RS2, RS3). A central axis of the first recess portion (RS2, RS3) may be spaced a first distance (d2, d3) in the second direction (Y) from a central axis of one of the first fin patterns (105B-105C). The first planar portion (FP1, FP2) may have a first width (W1, W2) in the second direction (Y) and may be larger than the first pitch (P1). The first distance (d2, d3) can be about 0.8 times to about 1.2 times the first pitch (P1). |