| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06506
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-12015
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0658
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-023
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-1565
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1093 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-32 |
| filingDate |
2021-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d0978c1049b58ab3203a3a961a7a94e7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d73190ccea636d08a2a9e6ca18eeddf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7d5401d5971c5ba3513eb3dfa9ae4713 |
| publicationDate |
2022-02-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102021106216-A1 |
| titleOfInvention |
Non-volatile memory device and storage device including the non-volatile memory device |
| abstract |
A non-volatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from a controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal and performs a phase calibration operation on the second signal based on a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals. |
| priorityDate |
2020-08-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |