http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102021100870-A1

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filingDate 2021-01-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89ac37a15b41608ebd73df1a47d3b489
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publicationDate 2021-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber DE-102021100870-A1
titleOfInvention HYBRID LAYOUT LAYOUT, PROCESS, SYSTEM AND STRUCTURE
abstract One method of generating an IC layout diagram includes lining up a first row of cells and a second row of cells along a boundary, the first row including first and second active layers and the second row including third and fourth layers wherein the active layers extend along a row direction and have width values. The active layers are covered with a first to fourth rear via region, the width value of the first active layer being greater than the width value of the third active layer, a width value of the first rear via region being greater than a width value of the third rear via region and a value of a distance from the first active layer to the boundary is smaller than a minimum distance rule for metal-like defined areas. Lining up the first row and the second row and / or covering the active layers with the back-side via regions are carried out by a processor.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021240903-A1
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priorityDate 2020-05-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 32.