Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1079 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2029-7858 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1033 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82385 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66553 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
filingDate |
2020-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_641271c29858c8ca6f63d5157d045820 |
publicationDate |
2021-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
DE-102020119940-A1 |
titleOfInvention |
MULTIPLE GATE TRANSISTOR STRUCTURE |
abstract |
A semiconductor device according to the present disclosure has a first channel element having a first channel portion and a first connection portion, a second channel element having a second channel portion and a second connection portion, a gate structure surrounding the first channel portion and the second channel portion and an interior spacer feature disposed between the first connection portion and the second connection portion. The gate structure has a gate dielectric layer and a gate electrode. The gate dielectric layer extends partially between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion. The gate electrode does not extend between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion. |
priorityDate |
2020-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |