| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f47985b7c371b565f319708450999686 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0692
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-74
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7404 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-402
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0262
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7436
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0259
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41716
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0839
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-87
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02H9-046
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7408 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02H9-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-74 |
| filingDate |
2020-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6e347443bca556e78393fc0783f1f422
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_08d5ae3f576bfc3f0fffb4ee8311e75f |
| publicationDate |
2020-12-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102020109110-A1 |
| titleOfInvention |
HIGH VOLTAGE TOLERANT CIRCUIT ARCHITECTURE FOR APPLICATIONS SUBJECT TO ELECTRIC OVERLOAD FAULT CONDITIONS |
| abstract |
A semiconductor die with a high voltage tolerant electrical overload circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor comprises a first thyristor and a resistive thyristor electrically coupled in a stack between the signal pad and the ground pad, which improves the withstand voltage of the circuit relative to an implementation with only the thyristor. Furthermore, the ohmic thyristor has a PNP bipolar transistor and an NPN bipolar transistor, which are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This enables the ohmic thyristor to have both thyristor characteristics and ohmic characteristics based on a level of current flow. |
| priorityDate |
2019-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |