http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102020105664-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28132 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32137 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32136 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3086 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2020-03-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-04-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_68298e8e373a8c0ab442b9ee65fd5848 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_753dc01dee707a1cdc034f8ab75f927c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_05190d504ba2ed0667330d6a40ff4759 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aab6434c61989ffdf99a82aa06189322 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f776b431dcec0cbf1413445f9ee587f9 |
| publicationDate | 2022-04-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102020105664-B4 |
| titleOfInvention | GATE FORMATION PROCESS |
| abstract | Method comprising: providing a workpiece (200) having a substrate (202) and a plurality of semiconductor fins over the substrate, each of the plurality of semiconductor fins being spaced from another of the plurality of semiconductor fins by an isolation feature (206); depositing a gate material layer (208) over the workpiece (200), the gate material layer having a first thickness over a top surface of the plurality of semiconductor fins; forming a patterned hard mask (220) over the gate material layer (208), the patterned hard mask (220) having a first plurality of elongate features and a second plurality of elongate features; performing a first etch process (300) using the patterned hard mask (220) as an etch mask through the gate material layer (208) to form a trench (241-243) extending through about 90% to about 95% of the first thickness extends to a top surface of the plurality of semiconductor fins; performing a second etch process (400) using the patterned hard mask (220) as an etch mask to extend the trench (241-243) to a top surface of the isolation feature (206); and performing a third etch process (500) using the patterned hard mask (220) to extend the trench (241-243) into the isolation feature (206), wherein the first plurality of elongate features have a first spacing dimension and the second plurality of elongate features have a second spacing dimension that is greater than the first spacing dimension, wherein the first etching process (300) includes the use of carbon tetrafluoride and a pressure of between about 5.3 Pa and about 13.3 Pa, wherein the first etch process (300) does not use oxygen gas. |
| priorityDate | 2020-02-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 68.