| abstract |
Wafer level chip scale package comprising: a plurality of RDL traces (18) connected to a silicon wafer (10) through openings through a first polymer layer (16) to metal pads (12) on a top surface of the silicon wafer (10); a plurality of UBM layers (22) each contacting one of the plurality of RDL traces (18) through openings in a second polymer layer (20) over the first polymer layer (16); a plurality of solder bumps (24) each on a UBM layer (22); a metal plating layer (40) under the first polymer layer (16) and not contacting any of the plurality of RDL traces (18); and at least one separator lying between at least two of the plurality of RDL traces (18), the at least one separator having a metal border (42, 45) in a region between two adjacent RDL traces (18), the metal border (42 , 45) is in electrical contact with the metal plating layer (40), or wherein the at least one separator between the at least two of the plurality of RDL traces (18) has air gaps between two adjacent RDL traces (18), the air gaps comprising the metal plating layer (40) do not contact. |