| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4094
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4097
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0694 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-404
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-488
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-315
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-0335
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-05 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate |
2019-03-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e001144b7b6bee9aa1593d5efdc7170f |
| publicationDate |
2019-10-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102019108034-A1 |
| titleOfInvention |
EMBEDDED MEMORY IN THREE-DIMENSIONAL INTEGRATED CIRCUIT |
| abstract |
Here are described devices, methods and systems associated with a memory circuit in a three-dimensional (3D) integrated circuit (IC). A control circuit of the memory circuit may include logic transistors in a logic layer of the 3D-IC. The control circuitry may further include one or more interconnects (eg, local or global interconnects) and / or other devices in one or more front metal layers of the 3D IC. The memory circuit may further include a memory array in backside metal layers of the 3D IC. The memory array may be formed in the backside metal layers that are closest to the logic layer. Other embodiments may be described and claimed. |
| priorityDate |
2018-04-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |