Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a68790a12228f5b99e176e8aacff640a |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T2200-28 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T1-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3836 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T1-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T15-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T15-005 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-4843 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T15-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T15-506 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-163 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3877 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3881 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06T1-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06T15-06 |
filingDate |
2019-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_51c006dbb679b755517c7f8f037f8060 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ec7ba3c0af4b32fa57829233fe46461f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b6789a236f1245f10665f4c81c68dd85 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4ff4f207818ead76a0d0953648458ef0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_06c89e8a21e9469267e22167b5c0add2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cbf74440a04c7ef4c479781f246c2082 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1ed4999a93b3576f3fcf7adb2469bac0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_45df9226b373380a1de0b39c3893e7e2 |
publicationDate |
2020-02-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
DE-102019103326-A1 |
titleOfInvention |
ROBUST, EFFICIENT MULTIPROCESSOR-COPROCESSOR INTERFACE |
abstract |
Systems and methods are provided for an efficient and robust multiprocessor coprocessor interface that can be used between a streaming multiprocessor and an acceleration coprocessor in a GPU. To speed up a particular operation using the coprocessor, according to one implementation example, the multiprocessor issues a series of write instructions to write input data for the operation to locations accessible to the coprocessor, and issues an instruction to the coprocessor to execute the particular one And then issue a series of read instructions to read operation result data from locations accessible to the coprocessor to locations accessible to the multiprocessor. |
priorityDate |
2018-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |