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filingDate 2018-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_af9c153ea0cdd2a3ca8fcc2fc047600b
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publicationDate 2020-02-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber DE-102018122614-A1
titleOfInvention Cell boundary structure for embedded storage
abstract Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer and associated manufacturing methods. In some embodiments, a separation structure is fabricated in a semiconductor substrate to separate a memory area from a logic area. A memory cell structure is fabricated on the memory area, and a dummy structure is fabricated on the separation structure. A boundary sidewall spacer is made to cover the dummy structure. A dielectric protective layer is made on top of the boundary sidewall spacer. The boundary sidewall spacer and the dielectric protective layer provide a flat boundary sidewall that is not damaged during the production of the logic element structure and thus no high-k etch residue when producing the logic element structure with the HKMG technology (HKMG: high-k metal Gate).
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102020100603-B3
priorityDate 2018-08-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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