| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36f8253f3d0d59bcd9259217d4385d10 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-2602 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-25
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M13-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1048
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0246 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-16 |
| filingDate |
2016-12-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2b9a84360e0b57575e025f1c1b347a3e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_95a47abed035a944e9d1681e77e87a4c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f3faaeb72d710e3e52b1e2e380b0b85b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_54ee0928ac3357941ad7d7e414e38f25
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_97c1e0c5ddc91935c360ac508f04b2b8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_72fcdfef51198ca074d12152dfd40167 |
| publicationDate |
2022-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102016123689-B4 |
| titleOfInvention |
Memory circuit and method of operating a memory circuit |
| abstract |
A memory circuit (100) comprising: a plurality of electrically programmable memory cells (102) arranged along a plurality of rows and a plurality of columns in an electrically programmable non-volatile memory cell array; a plurality of word lines (114), each word line (114) being coupled to a plurality of word sections of the plurality of memory cells (102), each word section being adapted to store a data word (D); and at least one overlay word line (114o) coupled to a plurality of overlay sections, each overlay section comprising a plurality of overlay memory cells (1020), each of the plurality of overlay sections having an overlay word (A) written therein; wherein the memory circuit (100) is adapted to read for each of the plurality of word lines (114) from each of the word sections simultaneously with an overlay section of the plurality of overlay sections, whereby as an output of the read operation a result of an on the data word (D) and the overlay word ( A) performed logic operation is provided. |
| priorityDate |
2016-12-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |