| abstract |
A circuit comprising: an normally on transistor (DMTR) having a first source / drain node, a second source / drain node, a first gate (G1) and a second gate (G2); a first normally off transistor (EMTR1 ) comprising a third source / drain node and a fourth source / drain node and a third gate (G3), the third source / drain node being coupled to the first source / drain node; a second normally-off transistor (EMTR2) having a fifth source / drain node and a sixth source / drain node and a fourth gate (G4), the fifth source / drain node being coupled to the second source / drain node, the the first, the second, the third and the fourth gate (G1-G4) are coupled to different potential nodes which are designed to be controlled independently, the third gate (G3) and the first gate (G1) having separate potential nodes first controller (21) are coupled, andwhere in which the fourth gate (G4) and the second gate (G2) are coupled to separate potential nodes of a second controller (22). |