| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05572
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05569
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-94
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05147
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3192
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05124 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2858 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-544
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 |
| filingDate |
2016-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a6722049098196db4cb2d85be3965786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5cb24b2cfcec8d620b1b9fc4cce3311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89965a3d7981209774823030f3accd7a |
| publicationDate |
2017-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102016118311-A1 |
| titleOfInvention |
ESD-RESISTANT BACKEND STRUCTURES WITH NANOMETER DIMENSIONS |
| abstract |
Some embodiments relate to a semiconductor device on a substrate. An interconnection structure is disposed above the substrate, and a first conductor pad is disposed over the interconnection structure. Above the interconnect structure is disposed a second conductor pad spaced from the first conductor pad. Above the interconnect assembly is disposed a third conductor pad spaced from the first and second conductor pads. Above the interconnect assembly is a fourth conductor pad spaced from the first, second and third conductor pads. A first ESD protection element is electrically coupled between the first and second conductor pads; and a second ESD protection element is electrically coupled between the third and fourth conductor pads. A first device under test is electrically coupled between the first and third conductor pads; and a second device under test is electrically coupled between the second and fourth conductor pads. |
| priorityDate |
2015-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |