| abstract |
A semiconductor device includes: a first memory cell (MC1), a bit line, and a second memory cell (MC2). The first memory cell (MC1) has a first layer structure comprising a first memory layer (ME, 142, 142A, 142B) between a first heater electrode (HE1) and a first Ovonic threshold switching device. The bit line is on the first memory cell (MC1). The second memory cell (MC2) is on the bit line and has a second layer structure comprising a second memory layer (ME, 152, 152A, 152B) between a second Ovonic threshold switching device and a second heating electrode (HE2). The first and second layer structures are symmetrical with respect to the bit line. |