http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102015208657-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a2bcaf91101a370a3d64e3190366357f http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6af9a57049d2d91c036d4f5ab49154cb |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-03 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5223 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-55 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B53-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0805 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11512 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-08 |
| filingDate | 2015-05-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_245ef67a18ac153da028c4e2500dab14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_22ebe1fe0efd6691e3651bc9b65a09fe http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cc7468b5002776ac8dce5a55269f4a63 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4b802ff9c57d98bb89d13d50e77f10fc |
| publicationDate | 2018-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102015208657-B4 |
| titleOfInvention | Semiconductor structure comprising capacitors with different capacitor dielectrics, and method for their production |
| abstract | A method comprising: Providing a semiconductor structure (100, 600) comprising a transistor (1010) and a first interlayer dielectric (110) overlying a semiconductor substrate (101); Forming a first electrode (111) of a first capacitor (112) over the first interlayer dielectric (110), the first capacitor (112) being a decoupling capacitor of an integrated circuit; Depositing a layer (201) of a substantially non-ferroelectric first dielectric material over the first electrode (111) of the first capacitor (112) and the first interlayer dielectric (110); Depositing a layer (202, 701) of an electrically conductive material over the layer (201) of the first dielectric material; Forming a second electrode of the first capacitor and a first electrode of a second capacitor of the layer of electrically conductive material; Depositing a layer (401) of a ferroelectric second dielectric material and forming a second electrode (402) of the second capacitor (303) over the second dielectric material layer (401) after forming the second electrode (301) of the second first capacitor (112) and the first electrode (302) of the second capacitor (303), and Forming a nonvolatile memory cell (1000) of the integrated circuit, the nonvolatile memory cell (1000) comprising the transistor (1010) and the second capacitor (303), the second capacitor (303) being electrically connected to the transistor (1010) , |
| priorityDate | 2014-06-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 67.