| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36f8253f3d0d59bcd9259217d4385d10 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41766
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1095
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26586
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-404
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7823
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-765
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0661
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7825
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66704 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-765 |
| filingDate |
2015-02-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2016-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_78e39ab23412da5e8687cd7d49b61423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_39fdaba8826e38a4bd75e15831007bce
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5f95338ee0e8daf980c5d4acc1f9295c |
| publicationDate |
2016-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102015102115-B3 |
| titleOfInvention |
SEMICONDUCTOR DEVICE WITH A TRANSISTOR ARRAY AND A CLOSING AREA AND METHOD FOR PRODUCING SUCH A SEMICONDUCTOR DEVICE |
| abstract |
A semiconductor device (1) formed in a semiconductor substrate (100) having a first main surface includes a transistor array (10) and a termination region (20). The transistor array (10) comprises a source region (201), a drain region (205), a body region (220), a drift zone (260) and a gate electrode (210) on the body region (220). The gate electrode (210) is configured to control a conductivity of a channel formed in the body region (220). The gate electrode (210) is provided in first trenches (212). The body region (220) and the drift zone (260) are arranged along a first direction between the source region (201) and the drain region (205), wherein the first direction is parallel to the first main surface. The body portion (220) has a shape of a first ridge extending along the first direction. The termination region (20) includes a termination trench (272), wherein a portion of the termination trench (272) extends in the first direction, a length of the termination trench (272) is greater than a length of the first trenches (212) and the length along the first direction is measured. |
| priorityDate |
2015-02-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |