http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102014221371-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6af9a57049d2d91c036d4f5ab49154cb |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40111 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28185 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-516 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0922 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78391 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-105 |
| filingDate | 2014-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-04-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_14ac756cf99de3875e3f6a87e5fb5d38 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6b1ec268d6906e637acbaabfece83803 |
| publicationDate | 2018-04-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102014221371-B4 |
| titleOfInvention | A method of forming a semiconductor circuit element and semiconductor circuit element |
| abstract | A method of forming a semiconductor circuit element (100; 200; 300) having a first semiconductor device (120; 220; 320) and a second semiconductor device (110; 210; 310), the method comprising: Providing the first semiconductor device (120; 220; 320) in and on a first active region (122) of a semiconductor substrate (102), the first semiconductor device (120; 220; 320) having a first gate structure (121 ';221; 321) a first gate dielectric layer (124); and Providing the second semiconductor device (110; 210; 310) in and on a second active region (112) of the semiconductor substrate (102) adjacent to the first active region (122), wherein the second semiconductor device (110; 210; 310) comprises a second gate structure (110; 111, 211, 311) having a second gate dielectric layer (114), wherein the first gate dielectric layer (124) is formed in the first active region (122) by providing a buried ferroelectric material (124), wherein the second gate dielectric layer (114) is formed by forming a high-k material (142) other than the ferroelectric material (124) over the second active region (112), and wherein burying the ferroelectric material (124) in the first active region (122) comprises forming a recess (132) in the first active region (122), forming a film of amorphous material (124) in the recess (132), wherein the amorphous material film (124) exhibits a ferroelectric behavior in a crystalline phase, forming a capping layer (138) on the amorphous material film (124), and crystallizing the amorphous material film (124) in the recess (132 ). |
| priorityDate | 2014-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 34.