| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31053
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823878 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31055
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0928 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate |
2014-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d05eed88f2692e35cf089cee4f365c3e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dffcbe1ca2589b921ebbbf56cf34f0e2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8f1f6aa869e43758219d47e5c62de5dc |
| publicationDate |
2015-07-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102014119156-A1 |
| titleOfInvention |
Composite Structure for Gate Layers Inter-layer dielectric |
| abstract |
A method of forming an integrated circuit device includes forming dummy gates on a semiconductor substrate, depositing a first dielectric layer on the dummy gates, chemo-mechanical polishing to lower the first dielectric layer to the height of the dummy gates, etching to Recessing the first dielectric layer below the height of the gates, depositing one or more further dielectric layers on the first dielectric layer, and chemo-mechanical polishing to lower the one or more further dielectric layers to the height of the gates. The method provides an integrated circuit device having metal electrodes and a gate level intra-level dielectric comprising a capping layer. The cap layer resists etching and maintains the gate height through a gate replacement process. |
| priorityDate |
2013-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |