| abstract |
A power semiconductor chip package includes a housing (360), a semiconductor die (310) embedded in the housing (360) and at least four terminals (371, 372, 373, 374) partially embedded in the housing (360) and partially to the outside of the housing (360) to expose. The semiconductor chip (310) includes a first doping region in ohmic contact with a first metal layer (351), a second doping region in ohmic contact with a second metal layer, and a plurality of first trenches including gate electrodes and first field electrodes that electrically isolate from the gate electrodes are. A first terminal (371) of the four terminals is electrically connected to the first metal layer (351), a second terminal (372) of the four terminals is electrically connected to the second metal layer, a third terminal (373) of the four terminals is electrically connected to the first terminal Gate electrodes of the first trenches connected and a fourth terminal (374) of the four terminals is electrically connected to the first field electrodes of the first trenches. |