http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102013105504-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0657 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41783 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41741 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41758 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-535 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-739 |
| filingDate | 2013-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2016-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fd8d43362ded6083a0dddb71ec7d6ea7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8520d0eeeb33b092292b36dada9b69c5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_08da4b1e5f68c892cdc012c587f1859d |
| publicationDate | 2016-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102013105504-B4 |
| titleOfInvention | Vertical Tunnel Field Effect Transistor Cell |
| abstract | A semiconductor device (200) comprising: a substrate (210); a bulge structure (220) disposed over the substrate (210) and protruding from the plane of the substrate (210); a gate stack (250) disposed over the substrate (210), the gate stack (250) having a planar portion symmetrical about the central axis of the bulge structure (220) and parallel to the surface of the substrate (210), and a gating surface surrounding a central portion of the bulge structure (220); and a source region (260) disposed as an upper portion of the bulge structure (220) and overlapping an upper portion of the gate surface of the gate stack (250); a drain region (240) disposed over the substrate (210) adjacent to the bulge structure and symmetrical about the central axis of the bulge structure (220) and to a lower portion of the bulge structure (220) raised drain region extends; a source contact (280) disposed on the source region (260); a gate contact (282) disposed on the planar portion of the gate stack (250); a drain contact (284) disposed on the drain region (240); and wherein the source contact (280) is aligned with two other source contacts (280) of two adjacent semiconductor devices such that each of the source contacts (280) is located in one of three corners of an equilateral triangle. |
| priorityDate | 2013-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 37.