http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102013100423-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_59c820ad08f8533c7440ae1d9235b168 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7397 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7811 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66734 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-739 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-765 |
| filingDate | 2013-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2017-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fb40761403760ec957ee102977e0a357 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6cfdcc2b8f93a54b10ae3a220f140c42 |
| publicationDate | 2017-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102013100423-B4 |
| titleOfInvention | Semiconductor transistor with trench contacts and manufacturing method therefor |
| abstract | A method of manufacturing a semiconductor transistor device, comprising: - Providing a semiconductor body (40) having a vertical direction defining the first surface (101); - defining an active area (110), a first contact area (120) and a second contact area (130); - Forming vertical trenches in the semiconductor body (40), so that in a vertical cross-section, a first vertical trench (150), a second vertical trench (160) and a third vertical trench (170) from the first surface (101) in the semiconductor body (40), wherein the first vertical trench (150) is formed in the active region (110), the second vertical trench (160) is formed in the first contact region (120), and the third vertical trench (170) is formed in the second Contact area (130) is formed; Forming respective first conductive regions (1, 1 ', 1'') in the second vertical trench (160) and in a lower portion of the first vertical trench (150) such that the first conductive region in the second vertical trench (160) extends above the first surface (101); Forming respective second conductive regions (2, 2 '') in an upper portion of the first vertical trench (150) and in an upper portion of the third vertical trench (170); Forming an insulating layer (6) in the first vertical trench (150), in the third vertical trench (170) and on the first surface (101) such that the insulating layer (6) has a first recess (51) above the second conductive region of the first a first vertical trench (150), a second recess (71) above the second conductive region of the third vertical trench (170), and a protrusion above the first conductive region of the second vertical trench (160); - depositing a polycrystalline semiconductor layer (7) on the insulating layer (6); and - Anisotropic etching of the polycrystalline semiconductor layer (7) to partially remove the insulating layer (6) in the second recess (71), while the insulating layer (6) below the first recess (51) remains covered. |
| priorityDate | 2012-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.