| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a68790a12228f5b99e176e8aacff640a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-563
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15174
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13147
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73204
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13139 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3107
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0655
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49827 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 |
| filingDate |
2013-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9ebedf5762a1df0f78e8e94383306085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8ba8b04de40c2b8530fa286c13905ff |
| publicationDate |
2014-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102013019513-A1 |
| titleOfInvention |
THREE-DIMENSIONAL STRUCTURE OF SILICON IMPLEMENTS |
| abstract |
Embodiments of the present invention include multi-chip devices that are disposed together in the same package. The plurality of chips are arranged on an intermediate element, which is then arranged on a housing substrate. The intermediate element comprises a semiconductor substrate, such as silicon, with feedthroughs extending from a front surface of the intermediate element to a rear surface of the intermediate element. The intermediate element may be a passive intermediate element or an active intermediate element. An active intermediate element contains the function of one or more chips and thus reduces the number of chips arranged on the active intermediate element. |
| priorityDate |
2012-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |