http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102012224361-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4074 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L5-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-018521 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1057 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1084 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4074 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0185 |
| filingDate | 2012-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b6f7418368268d22895eaa80616e6ff4 |
| publicationDate | 2022-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102012224361-B4 |
| titleOfInvention | Level shifter circuit and semiconductor integrated circuit |
| abstract | Level shifter circuit, which includes: a first transistor (101, 410) comprising: a first gate electrode (405); a second gate electrode (398); a source electrode (416a); and a channel region (408) between the first gate electrode (405) and the second gate electrode (398); and an inverter circuit (102) electrically connected to the first transistor (101), the inverter circuit (102) having an input terminal (IN) and an output terminal (OUT), wherein the first gate electrode (405) and the source electrode (416a) are configured to be supplied with a first power supply potential (V1), wherein the second gate electrode (398) is configured to be supplied with a second power supply potential (V2), wherein the inverter circuit (102) is configured to be supplied with a third power supply potential (V3) as a power supply potential, wherein the input port (IN) is configured to be supplied with an input signal, wherein the third power supply potential (V3) or a potential obtained by subtracting an amount of change in a threshold voltage of the first transistor (101, 410) from the first power supply potential (V1) is supplied as a power supply voltage to the inverter circuit (102), wherein an output signal (OUT1) is output from the inverter circuit (102), and wherein the channel region (408) of the first transistor (101, 410) is formed in an oxide semiconductor film. |
| priorityDate | 2011-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 59.