| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66803
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-283 |
| filingDate |
2012-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3f01682eeaecc5bac09a769243d6aba2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ac3c9365ac185348d99c5460aa0b0e23
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e08d91ff19fce642276d4cd68e163970
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_48da524752ec4021b3315ffaa658bece
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4d1313d8bfcce1d3c9f574e3ee09fe93
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cf848ccd340484a8d2f4bb368aeb51a7 |
| publicationDate |
2013-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102012217491-A1 |
| titleOfInvention |
Reduction of parasitic capacitance in FinFETs by using an air gap |
| abstract |
A transistor, such as a FinFET, has a gate structure disposed over a substrate. The gate structure has a width, and also a length and a height, which define two opposite side walls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region which passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and acts to reduce the parasitic capacitance of the transistor. At least one method of manufacturing the transistor is also disclosed. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11031481-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10756196-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11094796-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10756197-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102017126049-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102019133935-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102019133935-B4
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10510860-B2 |
| priorityDate |
2011-10-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |