http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102011016366-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7e6741a754a494546d3c52b259f083b7 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02502 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02433 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0245 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02381 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B29-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02661 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0262 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02461 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B25-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02543 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C30B25-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-205 |
| filingDate | 2011-04-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f2201660c08f9615310c97f0f9a6761b |
| publicationDate | 2012-10-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102011016366-A1 |
| titleOfInvention | Process for the preparation of a III / V-Si template |
| abstract | The invention relates to a method for producing a monolithic template comprising a Si wafer with a layer of a III / V semiconductor epitaxially applied to a surface of the Si wafer, the III / V semiconductor having a lattice constant which is less than 10% of that of Si A) optionally the surface of the Si wafer is deoxidized, B) optionally a Si layer is epitaxially grown on the surface of the deoxidized Si wafer, C) optionally the surface of the Si wafer or the surface of the Si layer subjected to an etching and / or baking process step, D) on the surface of the Si wafer or in the course of one of the steps A) to C) surface is at a wafer temperature of 350-650 ° C, a growth rate of 0.1-2 μm / h and a layer thickness of 1-100 nm, a layer of a III / V semiconductor grown epitaxially, E) on the layer obtained in step D) t is at a wafer temperature of 500-800 ° C, a growth rate of 0.1-10 microns / h and a layer thickness of 10-150 nm, a layer of a III / V semiconductor, equal to or different from that in step D. ) applied III / V semiconductor, grown epitaxially. |
| priorityDate | 2011-04-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 58.