| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_364d1f4c8e0186b6665af130449dc42a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2223-54426
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-68381
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-6835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05567
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-05 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-544
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-6835 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-58
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-544
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 |
| filingDate |
2011-03-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2034ec8b2a3e82d8c0e8b010fea63ef4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b6adf4de3fb7084cbb74e6e0108d2ea6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_30f1ed3b9776f899a71ee636379fdfa7 |
| publicationDate |
2012-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
DE-102011013228-A1 |
| titleOfInvention |
Method of manufacturing a semiconductor device for 3D integration |
| abstract |
In the method of manufacturing a semiconductor device, a substrate (1) of semiconductor material having a main side (2) is provided. A conductive region (23) of patterned metal layers (3) is fabricated in an intermetal dielectric (8) over the main side. Then, a first stop layer (13) and a second stop layer (15) of a material which can be selectively removed with respect to the first stop layer are applied. Thereafter, a handling wafer (16) is attached to the conductor area. The second stop layer can in this case be used in particular as a connecting layer. The second stop layer is arranged in this way between the handling wafer and the conductor region. A via (17) to one of the metal levels is made through the substrate. Then, the handling wafer is removed, and this process step ends on the second stop layer. The second stop layer is selectively removed to the first stop layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2015097002-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2889901-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10468541-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102014104239-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9786487-B2 |
| priorityDate |
2011-03-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |