http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102010029140-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_39d0c87b621374b0db45b24530018880 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03B5-1243 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03B5-1228 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03B5-1215 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-0233 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03B5-12 |
| filingDate | 2010-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b1271cc4d39f3cc4d3698a113e7d924d |
| publicationDate | 2011-11-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102010029140-A1 |
| titleOfInvention | Built-in CMOS wide band clock with differential design |
| abstract | A wide band differential clock having a voltage controlled oscillator for generating a differential oscillator signal, comprising two cross-coupled PMOS transistors each having a source, drain, and gate, comprising a balanced capacitance diode circuit having a control voltage adjustable Comprising capacitance acting between the two drain terminals, comprising an inductor circuit connected in parallel with the capacitance diode circuit having a center tap, and comprising two output terminals for sampling the differential oscillator signal, which are each connected to one of the drain terminals, with a positive supply contact and a negative supply contact and a bias current source for biasing the oscillator with a quiescent current, its first pole to the positive supply contact and its second pole to the source-on terminals of the PMOS transistors is connected, wherein an adjustable diode block is provided, which comprises a plurality of NMOS transistors, each having a source terminal, a drain terminal and a gate terminal, wherein the drain terminals with the center tap the inductance circuit and its source terminals are connected to the one negative supply contact, wherein each of the NMOS transistors is assigned in each case a control circuit which, depending on a binary programming signal, the respective gate terminal either with the respective drain terminal or with the respective source Connection connects. |
| priorityDate | 2010-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID426323534 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID10418702 |
Total number of triples: 16.