http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102008041324-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fd446fb0d73aa96d044fea2eaa3c8ebc |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318516 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-22 |
| filingDate | 2008-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2017-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_111fe5db1a4a64f1fe833446bd5de144 |
| publicationDate | 2017-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102008041324-B4 |
| titleOfInvention | Test system and method for testing FPGA test objects and an FPGA test object |
| abstract | Method for the production test of a test object equipped with at least one FPGA unit (1), wherein the FPGA unit (1) is coupled to a configuration memory (3) in which at least operating program data are input in a preset readout direction (A1) ( ) are readably stored, so that during startup of the FPGA unit (1) in a normal operation the operating program data is loaded, which are stored starting from a first end of the configuration memory (3), characterized in that during startup of the FPGA unit (1) for the production test of the test object from the configuration memory (3), test program data are loaded in the configuration memory (3) in an read-out direction (A2) (A2) opposite to the readout direction of the operating program data (FIG. ) are readable, for loading the test program data, the default readout direction (A1) for loading the operating program data is reversed before configuring the FPGA unit (1), wherein the preset readout direction (A1) for loading the operation program data by a defined level impressed on a configuration pin of the FPGA unit (1) is permanently set and the preset readout direction (A1) for loading the test program data by inverting This level is temporarily changed in the read-out direction (A2) by the configuration pin of the FPGA unit (1) is influenced by means of a test object (10) foreign to the test object. |
| priorityDate | 2008-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 21.