| abstract |
Thenpresent invention provides a multi-chip packaging structurencomprising: a substrate having a chip receiving cavity disposed within anupper surfacenof the substrate, and a first via hole structure,nwherein terminal contact traces under the first via structurenare formed. A first chip is within the receiving cavitynarranged, and a first dielectric layer is on the firstnChip and the substrate formed. A first conductive redistribution layernis formed on the first dielectric layer. A secondnDielectric layer is overnformed the first redistribution layer. A third dielectricnLayer is formed under a second chip. A second seniornRedistribution layer is formed under the third dielectric layer.nA fourth dielectric layer is under the second redistribution layerneducated. Conductive contact balls are with the first redistribution layernand the second redistribution layer. A surrounding materialnsurrounds the second chip. The second chip is through the firstnRedistribution layer, the second redistribution layer and the conductivenContact balls connected to the first chip. |