http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102007063640-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_69a4ae662cd6a46490ee45a70e85dc39 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T29-49117 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-30 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate | 2007-05-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2014-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a1ad2f1d12b0c5bc59572840d8b49037 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_acfb617647da67975f6047aa744be133 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9c5995fbdc448d4edbdabf4d16075fd0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_756b32ecf7b55beeef0ea601e214c56c |
| publicationDate | 2014-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102007063640-B4 |
| titleOfInvention | Integrated circuit with a memory cell arrangement |
| abstract | An integrated circuit having a memory cell array (100), the memory cell array (100) comprising: A plurality of memory cells arranged one above the other or in a fin structure (154); A switch structure with switch elements, wherein at least some of the switch elements are arranged one above the other or one above the other, wherein each switch element is assigned to a respective memory cell; Wherein the memory cell array (100) is a NAND memory cell array, the fin structure (154) extending in its longitudinal direction as a first direction, the fin structure (154) comprising: A first insulating layer (156); A plurality of first active regions (158) of a first plurality of memory cells coupled to each other in series connection in the first direction and disposed on or above the first isolation layer (156); A second insulating layer (160) disposed on or above the first active regions (158); A plurality of second active regions (162) of a second plurality of memory cells coupled to each other in series connection in the first direction and disposed on or above the second insulating layer (160); A plurality of charge storage layer structures (172) disposed at least adjacent to at least one sidewall of the fin structure (154) and covering at least a portion of the first active region (158) and at least a portion of the second active region (162); and A plurality of control gate layers (174) disposed adjacent to the charge storage layer structures (172); ... |
| priorityDate | 2007-04-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 45.